1. Field of the Invention
This invention relates to improvements in methods and apparatuses for dynamic information storage or retrieval, and more particularly to improvements in methods and circuitry for detection and correction of errors, especially in information storage and retrieval systems that use a magnetic data storage medium, and still more particularly to improvements in methods and apparatuses for improving data detection in dynamic information storage or retrieval systems of the type that use post-processor data detection techniques.
2. Relevant Background
Mass data storage devices may include, for example, hard disk drive apparatuses (HDA), or other similar data recording devices. Mass data storage devices include well known hard disk drives that have one or more spinning magnetic disks or platters onto which data is recorded for storage and subsequent retrieval. Hard disk drives may be used in many applications, including personal computers, set top boxes, video and television applications, audio applications, or some mix thereof. Many applications are still being developed. Applications for hard disk drives are increasing in number, and are expected to further increase in the future.
A typical hard disk drive includes one or more spinning discs that are coated with a magnetic material so that data can be written to and read from concentric rings in the magnetic media of the disk by one or more magnetic transducer devices that are located in proximity to the disc and selectively located to particular rings in which the data is written. Mass data storage devices may include other types of devices that are susceptible to the same type of error creating mechanisms as HDAs.
In the construction of the data channel used in hard disk drives, or the like, there has been significant recent interest in Partial Response Maximum-likelihood (PRML) signaling techniques. The most common PRML systems are PR4ML (a partial response class 4) and EPR4ML (extended partial response class 4). Maximum-likelihood detectors, which use a Viterbi algorithm, are generally used for these partial response channels.
Recently, an EPR4 channel has been introduced. In comparison to previously used PR4 partial response target, which is 1xe2x88x92D)*1+D), the EPR4 partial response target, which is 1xe2x88x92D)*1+D)2, where D is a delay operator, equal to ejwxcfx84, where w is frequency, and xcfx84 is delay time.
In such systems, the use of EPR4 Viterbi data detection techniques is widely employed. EPR4 Viterbi detectors are well known, and involve probabilistic techniques for determining data states in the data channel. As data rates increase in the data channel, it becomes increasingly difficult to distinguish adjacent data pulses, and the Viterbi techniques have been found to be very useful.
Unfortunately, significant errors still occur in data detection. For example, using EPR4 techniques, a bit error rate (BER) of about 10xe2x88x925 typically occurs. As the data packing densities are increased, the more difficult the accurate read back of the data becomes. For example, bit error rates (BERs) in the neighborhood of 10xe2x88x927, or better, are presently being expected of modern day HDA""s, and it is expected that this requirement will continue to become more stringent. However it has been observed that if the signal-to-noise ratio in a system could be reduced by even as little as, for example, 1 dB, the bit error rate can be improved by an order of magnitude improvement. Thus, even small improvements in the signal-to-noise ratio results in large improvements in the bit error rate using EPR4 detection techniques.
In the past, a typical EPR4 circuit would receive an input signal that has been amplified by a pre-amplifier from the data transducer of the storage device. The amplified signal is applied to an EPR4 equalizer that produces an output that is detected by an EPR4 Viterbi detector. The output from the EPR4 Viterbi detector typically contains the desired data which has been decoded using the above mentioned probabilistic techniques.
Partial response channels are subject to certain error-events. An error event occurs when the channel symbol that represents the polarity of a write current is misread. It should be noted that as data is written to the magnetic medium, it is written synchronously with a clock that requires the data at each clock cycle to assume a particular state. In addition, the nomenclature used to represent the write current sequence is referred to as xe2x80x9cnon-return-to-zeroxe2x80x9d or xe2x80x9cNRZxe2x80x9d notation. The number of MTR states is cut in half by using xe2x80x9cnon-return-to-zero-inversexe2x80x9d or xe2x80x9cNRZIxe2x80x9d notation, where a zero corresponds to no transition, and a one corresponds to a transition. Consequently, the initial coding done on data to be written is to NRZI data.
In many recent applications, maximum transition run length (MTR) coding has used to improve the performance of partial response channels. In MTR coding, a number of input bits are mapped to a larger number of possible bits. For example, a typical MTR code is a 16/17 coding in which 16 input bits are mapped to a 17-bit frame. Thus, after characterizing a magnetic recording partial response channel, a list of dominant error-events is compiled. Then, an MTR code is designed so that code mappings do not contain any dominant error-events. However, merely constraining the sequences to a given coding constraint is not enough to obtain a significant coding gain. Rather, a Viterbi detector which is matched to the combination of the channel and the code must be used to insure that the detected sequence is allowed by the constraint.
Additionally, MTR codes eliminate certain consecutive transition errors. By removing certain transitions possibilities, corresponding write current sequences are not allowed. Therefore, many of the dominant error-events at high densities are removed along with many other likely error-events. Such code reduces the number of transitions and increases the spacing between transitions.
Thus, MTR coding permits a predetermined number of consecutive transitions, and prohibits a predetermined number of consecutive non-transitions. A transition for purposes of MTR coding is either a transition from 0 to 1 or a transition from 1 to 0. The basic idea of MTR coding is to eliminate certain input bit patterns that would cause most error-events in a sequence detector. For example, a MTR (3:11) coding requires that no more than three consecutive input transitions occur, and that no input condition results in more than 11 consecutive time periods during which no transition occurs. This eliminates four or more consecutive transitions, and eliminates 12 or more non-transitions. With the MTR constraint, precompensation can be performed more accurately.
In general, the MTR constraint removes branches and/or states from the Viterbi detector for the channel. Therefore, MTR coding provides coding gain at high densities without adding complexity to the system. While MTR codes provide coding gain without adding complexity, a number of error conditions still remain, particularly in the presence of additive white Gaussian noise (AWGN) and media noise. Moreover, as the processing level is increased, several problems have emerged. For example, although the EPR4 channel yields better performance than the PR4 channel for higher recording densities, the complexity of the Viterbi detector used in an EPR4 channel increases by more than twice, and the maximum data rate decreases. In order to avoid these drawbacks, several techniques have been proposed.
One technique is the use of a post-processor. Since a post-processor can use the same metric as an EPR4 Viterbi detector, the criteria used to correct minimum distance error-events can be the same criteria as those used in an EPR4 Viterbi detector to select survivor paths. The main benefits to such post-processing approaches is reduced complexity in the feedback path associated with the updating process for the Viterbi detector, allowing for higher channel rates.
Thus, in order to enhance the BER performance, recently, post-processors have been incorporated with the Viterbi detector. An example of such post-processor is that shown in U.S. patent application Ser. No. 09/229,945, filed Jan. 13, 1999, entitled POST-PROCESSOR USING A NOISE WHITENED MATCHED FILTER FOR A MASS DATA STORAGE DEVICE, OR THE LIKE, assigned to the assignee hereof, and incorporated herein by reference. In said patent application, a post-processor was described that employed data filters to filter equalized or recreated write data after being read back from the memory media. The filter produced an error signal that was above a predetermined threshold when particular error events occurred. The error events that were selected were those that had the highest likelihood of occurring. By addressing those particular error events, the bit error rate (BER) of the system was greatly improved. However, in recent disk drives that have a high recording density, the media noise from the magnetic disk has become an important factor that is difficult to ignore.
The media noise arises primarily from written magnetic transitions, which typically have a zigzag transition geometry. The zigzag transition geometry produces position or pulse width uncertainties or xe2x80x9cJitterxe2x80x9d variations of read back signals. When media noise is dominant, it is difficult for such post-processors to improve performance, since the characteristic of media noise is quite different from white noise. The spectrum of the media noise is not white, and is dependent on the data pattern written on the magnetic disk.
Another technique that has been used to avoid the drawbacks encountered is to use parity values written to the disk in conjunction with the user data. The parity values may be generated in various ways, but, in general, the parity code bits generated represent certain characteristics of the data that is written so that when the data is subsequently read back from the disk, together with the prerecorded parity value, and a parity value is regenerated from the read back data, if a discrepancy exists, it can be assumed that an error has occurred in the read back data. The use of parity values, however, in the past has only provided an indication that an error has occurred, but does not usually enable the error position to be determined or the error to be corrected.
Recently, one or more parity bits have been used in conjunction with post-processing circuitry, but without any constraints being imposed on the run length encoding of the data written to the HDA. As a result, the post-processor must detect and correct a large number of various error conditions, necessitating very complex post-processing circuitry.
In light of the above, it is, therefor, an object of the invention to provide an improved method for performing error correction in writing data to and reading data from a mass data storage device.
It is another object of the invention to provide a method for including parity data in combination with maximum transition run length constraints on data that is written to and read from a mass data storage device.
It is yet another object of the invention to provide a method for encoding data that includes parity code data in a system that has a MTR(3:11) code constraint.
It is still another object of the invention to provide a method and circuit for performing post-processing of data that includes parity information read from a mass data storage device, in which errors are detected and corrected using error filters to detect specific error sequences in conjunction with the recovered parity information.
We have found that by additionally including parity information in the post-processor, and more over including run length limited coding techniques, that the bit error rate can be significantly further reduced.
Thus, according to a broad aspect of the invention, a method is presented for writing data to a mass data storage device. The method includes applying a maximum transition run length code constraint to the data to be written and developing parity data based on the predetermined number of bits of the data to be written. The method also includes concatenating the parity data with the data to be written and writing the concatenated data to the mass data storage device. Developing the parity data may include developing three parity bits, a center one of the parity bits being a xe2x80x9cpadxe2x80x9d bit, wherein the xe2x80x9cpadxe2x80x9d bit is selected to avoid code constraint violations by the parity data concatenated to the data, to be written. The code constraint may be, for example, a MTR(3:k) code constraint.
According to yet another broad aspect of the invention, a post-processor is presented for use in a mass data storage device to which parity information has been written together with MTR encoded data. The post-processor includes an equalizer to equalize data and the parity information read back from the mass data storage device to an EPR4 target and a filter connected to receive data and parity information which has been read back from the mass data storage device and equalized to an EPR4 target to produce a maximum output in the presence of a predetermined error pattern. A parity checker produces an output if the recorded parity on the memory element does not match recalculated parity information, and a circuit corrects the read back data at a bit position indicated by the maximum value of the filter when the parity checker determines that the recorded parity and recalculated parity are different.
According to another broad aspect of the invention, a mass data storage device is presented which includes a circuit for encoding data to be written to the mass data storage device with at least a maximum transition run length constraint. A circuit determines parity information from, and associates the parity information with, the data to be written to a storage media of the mass data storage device. A circuit reads back the data and parity information from the storage media, and a parity checker recalculates parity information from the read back data. The parity checker produces an output indicating whether the read back parity and recalculated parity information do not match. A post-processor circuit including at least one filter detects an error pattern in the read back data, and to correct the read back data using the parity checker output if the error pattern is detected. The post-processor may include, for example, three filters to respectively determine the occurrence of ex=xc2x1{1}, ex=xc2x1{1,xe2x88x921}, and ex=xc2x1{1,xe2x88x921,1} error event contributors.
The parity information may be concatenated between adjacent data frames, and may include parity information about even bits in a data frame, parity information about odd bits in the data frame, and a pad bit. The pat bit may be configured to assure that no maximum transition run length code constraint is violated when the parity information is concatenated between adjacent data frames.